1. Field of the Invention
The embodiments of the invention provide a lock and key structure for three-dimensional chip connection and the process thereof where key studs on the first wafer contact conductors within the second wafer, and because the lock openings extend through an outer oxide, the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL) and at the back-end-of-the-line (BEOL).
2. Description of the Related Art
Three-dimensional (3D) chip integration presents many potential benefits for integrated circuit industries. For example, in 3D integrated circuits, each transistor may access a greater number of its nearest neighbors than a conventional two-dimensional (2D) circuit. This potentially allows each transistor or functional block to have a higher bandwidth and thus, in the aggregate, the device may operate properly at higher clock cycle rates. For 3D device integration (lamination of multiple wafers) there are several aspects that should be taken into consideration. The first concerns issues with interface bonding between the wafers, and the second concerns distortion and topography management.
Several different ways of integrating 3D chips are known, such as Cu—Cu compression, oxide-oxide (or polymer) bonding, etc. While each of the conventional methods has advantages for making 3D chips, conventional processes are monolithic, because the bonding is initiated either for metal or dielectric but not both. Since the interface needs both metal (via) and dielectric bonding, the monolithic methods inherently require a two step process to stitch the metal contacts or enforce the dielectric bonding. In this regard the monolithic approaches can be unreliable and complex. In addition, it is difficult to achieve sub-micron accuracy at the wafer level with monolithic bonding due to lack of constraints in either in-plane registration and/or topographical conformity.